The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a crystal region formed of a regrowth process.
Compound semiconductor devices that use a compound semiconductor material for the essential part of the device, are used extensively for various high speed semiconductor devices such as MISFET, HEMT or HBT. It should be noted that such a compound semiconductor material has a characteristic band structure that provides a very small effective mass of electrons. Particularly, a HEMT induces a two-dimensional electron gas in an undoped compound semiconductor layer acting as an active layer, along a heterojunction interface thereof at which the active layer contacts with another, doped compound semiconductor layer. In such a structure, the electrons are transported through the two-dimensional electron gas without experiencing substantial scattering by dopant atoms.
In such high speed compound semiconductor devices, the parasitic resistance of the current path through the device provides a substantial effect upon the operational speed of the device. When the source resistance or drain resistance of a FET such as HEMT or MESFET is increased, for example, the operational speed of the device is inevitably deteriorated even when the semiconductor device itself operates very fast. Further, the reduction of the source or drain resistance is essential for realizing a complementary compound semiconductor device that includes a P-channel compound semiconductor device and an N-channel compound semiconductor device. As is well known in the art, N-channel compound semiconductor devices operate very fast because of the small effective mass of the electrons in the compound semiconductor material, while P-channel compound semiconductor devices operate less fast because of the relatively large effective mass of the holes. In order to operate such complementary devices successfully, it is therefore necessary and desirable to increase the operational speed of the slower P-channel device such that the P-channel and N-channel devices operate at a generally identical speed. For this purpose, decrease of the source or drain resistance of the P-channel device is particularly important.
FIG. 1 shows the structure of a typical conventional HEMT.
Referring to FIG. 1, the HEMT includes a channel layer 13 of undoped GaAs provided upon a semi-insulating GaAs substrate 11, wherein a buffer layer 12 of undoped GaAs is interposed between the substrate 11 and the channel layer 13. On the channel layer 13, there is provided an electron supplying layer 14 of a wide gap material such as AlGaAs, wherein the electron supplying layer 14 is doped to the n-type and supplies electrons to the channel layer 13. Thereby, the electrons thus supplied form a two-dimensional electron gas 13a in the channel layer 13 along the interface between the layer 13 and the layer 14. Further, a cap layer 15 of GaAs is provided on the electron supplying layer 14 for protecting the same from oxidation, wherein the cap layer 15 is doped to the n.sup.+ -type for reducing the resistivity thereof as much as possible, and an opening 15a is provided on the layer 15 so as to expose the surface of the electron supplying layer 14 in correspondence to the channel region of the device.
On the exposed surface of the electron supplying layer 14, on the other hand, there is provided a Schottky electrode 16 as a gate electrode, and source and drain electrodes 18.sub.1 and 18.sub.2 are provided on the cap layer 15 at both sides of the gate electrode 16. Thereby, the thickness of the electron supplying layer 14 is set so as to provide a desired threshold voltage. Further, an insulation layer 17 of SiON covers the exposed surface of the cap layer 15.
In such a structure, electrons are injected to the two-dimensional electron gas 13a in the channel layer 13 from the source electrode 18.sub.1 via the cap layer 15 and further via the electron supplying layer 14, and are collected by the drain electrode 18.sub.2 via the electron supplying layer 14 and the cap layer 15, after passing through the channel region along the two-dimensional electron gas 13a. Thereby, the flow of the electrons through the channel region is controlled by a depletion region extending from the gate electrode 16, wherein the extent of the depletion region is controlled by a control voltage applied to the gate electrode.
FIG. 2 shows the structure of a DMT (doped-channel MIS-like FET), a type of MISFET designed to minimize the gate current in a conventional MESFET. In a MESFET, and also in a HEMT as well, in which the gate electrode is provided directly upon a doped channel layer or electron supplying layer, it should be noted that a gate current may cause a leak depending upon the voltage applied to the gate electrode.
Referring to FIG. 2, the DMT is constructed on a semi-insulating GaAs substrate 21 and includes an n-type GaAs channel layer 23, with an undoped GaAs buffer layer 22 intervening between the substrate 21 and the channel layer 23. In the DMT, an undoped AlGaAs layer 24 is further provided on the channel layer 23 as a barrier layer, and a cap layer 25 of n.sup.+ -type GaAs layer 25 is provided on the barrier layer 24. It should be noted that AlGaAs forming the barrier layer 24 has a bandgap much larger than that of GaAs and acts as an effective barrier against the electrons that may leak in the form of gate current. Further, the cap layer 25 is formed with a contact window 25a that exposes the surface of the barrier layer 24, and a Schottky electrode 26 is provided upon such an exposed surface of the barrier layer 24 as a gate electrode. Further, ohmic electrodes 28.sub.1 and 28.sub.2 are provided on the cap layer 25 at both sides of the gate electrode 26, as source and drain electrodes, and the exposed surface of the cap layer 25 is covered by an insulator layer 27 of SiON.
In operation, electrons are injected into the channel layer 23 from the source electrode 28.sub.1 and are recovered by the drain electrode 28.sub.2 after passing through the n-type channel layer 23 as indicated by arrows and broken lines in FIG. 2, wherein the flow of the electrons through the channel layer 23 is controlled by a depletion region extending from the gate electrode 26 as usual in a FET.
In the structure of FIG. 2, it should be noted that the metal elements such as Au and Ge cause a diffusion from the ohmic electrodes 28.sub.1 or 28.sub.2 into the layer 25 and further into the layer 24 as indicated by a hatched region. In such a diffusion process, the concentration level of the metal elements diminishes gradually toward the active layer 23, and the hatched diffusion region may not reach the active layer 23, depending upon the thicknesses of the layers 25 and 24. When this is the case, the injection of the carriers into the active layer 23 is substantially blocked by the barrier layer 24, and the current paths indicated in FIG. 2 by arrows are interrupted as indicated by cross marks. As the thickness of the barrier layer 24 determines the threshold voltage and the gate leak current of the device, it is not possible to reduce the thickness of the layer 24 as desired. The thickness of the barrier layer 24 is determined as a result of trade-off of the threshold voltage of the device and the gate leak current. Thus, the conventional DMT of FIG. 3 has suffered from the problem of large resistance of the current path through the device.
In order to inject the electrons into the channel layer 23 with reliability, the inventor has proposed to form a recessed structure in the device in correspondence to the source and drain regions as indicated in FIG. 3 by an etching process, such that a regrowth of a doped crystal region is made on such a recessed region as source and drain regions.
Referring to FIG. 3, the recessed region is formed at both sides of the gate electrode 26 so as to reach the channel layer 23, wherein the recessed region thus formed is defined by a bottom surface 23a formed at a level below the level of the top surface of the channel layer 23. As a result of the formation of the recess, it will be noted that a ridge structure is formed by the remaining layers 24 and 25.
In the structure of FIG. 3, it should be noted that there are provided n.sup.+ -type GaAs regions 29a and 29b epitaxially on the respective recessed surfaces 23a so as to fill the recessed regions thus formed, and the source and drain electrodes 28.sub.1 and 28.sub.2 are provided respectively on the foregoing n.sup.+ -type regions 29a and 29b. Thereby, the regions 29a and 29b are formed as a result of the regrowth process. As the n.sup.+ -type regions 29a and 29b reach the channel layer 23 in the structure of FIG. 3, the injection and recovery of the electrons to and from the channel layer 23 is achieved positively, and the source or drain resistance of the device is substantially reduced.
On the other hand, the structure of FIG. 3 has a drawback in that the channel layer 23 experiences etching when forming the recessed region, while such an etching tends to damage the recessed surface 23a of the channel layer 23. When the channel layer 23 experiences such a damage, the source or drain resistance of the device increases inevitably. Further, the level or vertical position of the surface 23a inside the channel layer 23 is difficult to control because of the absence of any etching stopper in the layer 23. In addition, such a structure tends to invite a short channel effect, particularly when the gate length is reduced for high speed operation, in that the electrons tend to flow through the channel layer 23 through a bottom part thereof as indicated in FIG. 4 by a broken line. It should be noted that such a current path at the bottom part of the channel layer may not be effectively interrupted even when a control voltage is applied to the gate electrode 26 so as to interrupt the carriers that flow along the top surface of the channel layer 23. Thus, the device of FIG. 3 tends to show a small threshold voltage. It should be noted that the foregoing problem of increased source resistance occurs not only in HEMTs or MISFETs but also in a HBT.
FIG. 4 shows an example of a conventional complementary compound semiconductor integrated circuit, wherein the illustrated example includes a first HEMT and a second HEMT on a common substrate, the first HEMT including a two-dimensional electron gas while the second HEMT including a two-dimensional hole gas.
Referring to FIG. 4, the complementary device is constructed upon a semi-insulating GaAs substrate 31 on which is provided a semi-insulating GaAs buffer layer 32 with a thickness of about 600 nm. The buffer layer 32, in turn, carries thereon a channel layer 33 of an undoped InGaAs with a thickness of 14 nm, and an electron supplying layer 34 of n-type AlGaAs is provided on the channel layer 33 with a thickness of 30 nm. Further, a contact layer 35 of n-type GaAs is provided on the electron supplying layer 34 with a thickness of 50 nm, wherein the contact layer 35 is formed with an opening 35a in correspondence to a first region A as indicated in FIG. 4 so as to expose the upper major surface of the electron supplying layer 34, and a Schottky electrode 35A is provided on the exposed surface of the electron supplying layer 34 as a gate electrode. Thereby, a two-dimensional electron gas 33a is formed in the channel layer 33 that has a larger electron affinity over the electron supplying layer 34, wherein the two-dimensional electron gas 33a is formed along the interface between the channel layer 33 and the electron supplying layer 34. Further, ohmic electrodes 35B and 35C are provided on the contact layer 35 in correspondence to the foregoing region A, for injecting and recovering electrons to and from the two-dimensional electron gas. In other words, an ordinary HEMT is formed in the region A of the device of FIG. 4.
In the complementary device of FIG. 4, it should be noted that an undoped InGaP layer 36 is provided on the contact layer 35 in correspondence to a region B that is defined adjacent to the region A as an etching stopper, and a buffer layer 37 of undoped GaAs is provided on the etching stopper layer 36 with a thickness of 100 nm. On the buffer layer 37, there is provided a channel layer 38 of undoped InGaAs with a thickness of 14 nm, and a hole supplying layer of p-type AlGaAs is provided on the channel layer 38 with a supplying layer 39 has a composition of Al.sub.0.7 -0.8Ga.sub.0.2 -0.3 As and provides a very large bandgap. Thereby, a two-dimensional hole gas 38a is formed in the channel layer 38 similarly to the case of the channel layer 33, along the interface between the layer 38 and the layer 39. Further, a Schottky electrode 39A is provided on the hole supplying layer 39 as a gate electrode, wherein a thin undoped GaAs layer 39a is interposed between the layer 39 and the gate electrode 39A for improving the breakdown characteristics of the device and for eliminating the gate current leak. In addition, ohmic electrodes 39B and 39C are provided on the hole supplying layer 39 at both sides of the gate electrode 39A, respectively as source and drain electrodes. As a result, it will be noted that a high hole-mobility transistor is formed in the region B of the device, wherein the high hole mobility transistor will be designated also as HEMT in the following description for the sake of simplicity.
As the effective mass of a hole is generally larger than the effective mass of an electron in a III-V compound semiconductor material, the mobility of a hole in the two-dimensional gas 38a is substantially smaller than the mobility of an electron in the two-dimensional electron gas 33a. Thus, the complementary device of FIG. 4 shows a problem that the operation of the hole HEMT in the region B cannot catch up the operation of the electron HEMT in the region A. As a result of such a difference in the mobility of carriers, there emerges a problem of increased resistance Rs in the device of FIG. 4, wherein the resistance Rs represents the resistance that a hole experiences between the source electrode 39B and the gate electrode 39A.
In order to eliminate the foregoing problem of conventional complementary HEMT, efforts have been made to reduce the distance between the source electrode 39B and the gate electrode 39A as much as possible so as to increase the operational speed of the hole HEMT in the region B as much as possible. However, such an approach has been difficult as long as the electrodes 39A is formed of a material different from the material that forms the electrodes 39A and 39C. In such a case, it is necessary to first form one of the electrodes such as the electrode 39A, followed by a deposition of an insulation layer so as to cover the electrode 39A. The other electrode is then formed by providing a contact hole in the insulation layer. However, such a fabrication process inevitably results in a structure in which the first electrode such as the electrode 39A is separated from the second electrode such as the electrode 39B by an insulation region, and is not suitable for forming the electrodes 39A and 39B with a minimum separation.
In order to overcome the foregoing problem, a structure shown in FIG. 5 is proposed, wherein those parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIG. 5, a conductor layer corresponding to the gate electrode 39A is deposited upon the layer 39a, followed by a patterning process to form the gate electrode 39A. Further, the semiconductor layer 39a as well as the semiconductor layer 39 underneath the layer 39a are removed by a dry etching process except for a region (39A).sub.1 located immediately under the gate electrode 39A. Thereby, the upper major surface of the channel layer 38 is exposed at both sides of the region (39A).sub.1. Next, crystal regions (39B).sub.1 and (39C).sub.1 both of p-type AlGaAs or GaAs are grown epitaxially on the exposed surface of the layer 38 by a MOCVD process such that the regions (39B).sub.1 and (39C).sub.2 are formed at both sides of the foregoing region (39A).sub.1.
In the structure of FIG. 5, it should be noted that each of the crystal regions (39B).sub.1 and (39C).sub.1 is formed of a single crystal of p-type AlGaAs or GaAs defined laterally by a crystal surface. For example, the region (39B).sub.1 is defined by crystal surfaces 39B.sub.-1 and 39B.sub.-2, while the region (39C).sub.1 is defined by crystal surfaces 39C.sub.-1 and 39C.sub.-2. Thereby, the crystal surfaces 39B.sub.-1 and 39B.sub.-2 or 39C.sub.-1 and 39C.sub.-2 are inclined with a predetermined angle with respect to the upper major surface of the channel layer 38 to form a generally trapezoidal shape when viewed in an elevational cross sectional view as indicated in FIG. 5. In FIG. 5, it will be noted that the top area of the trapezoid is smaller than the base area in each of the regions (39B).sub.1 and (39C).sub.1.
In such a structure, the electrodes 39B and 39C provided respectively on the regions (39B).sub.1 and (39C).sub.1 do not contact with the gate electrode 39A on the region (39A).sub.1, although the region (39B).sub.1 or (39C).sub.1 contacts with the region (39A).sub.1 at the base part thereof. As a result of such a construction, the separation between the electrode 39A and the electrode 39B or between the electrode 39A and the electrode 39C is minimized and the operational speed of the HEMT in the region B is maximized.
In the construction of FIG. 5, however, there exists a problem in that the exposed surface of the channel layer 38 may be contaminated at the time of the dry etching of the semiconductor layer 39, for example by oxygen or other contaminants such as C, Si, Cl, CH.sub.x, and the like, that are contained in the etching gas. It should be noted that the compound CH.sub.x is formed as a result of the reaction between C and H originated from CO.sub.2 and H.sub.2 O in the air. When the semiconductor region (39B).sub.1 or (39C).sub.1, is grown on such a contaminated surface, the contaminants inevitably induce a depletion region at the interface between the layer 38 and the region (39B).sub.1 or (39C).sub.1, while such a depletion region in turn invites an increase of the source resistance or drain resistance of the HEMT as a result of depletion of the carriers.
Conventionally, such a contamination has been removed by processing the exposed surface by NH.sub.4 S.sub.x, while such a processing tends to cause a deposition of S at the exposed surface of the layer 38. As S acts as a donor, the deposition of S does not cause any problem as long as an n-type layer is grown upon the exposed surface. However, when growing a p-type region (39B).sub.1 or (39C).sub.1 as in the present case, the contamination of the exposed surface by S invites an unwanted formation of p-n junction at the interface. Such a formation of the p-n junction of course invites an increase of the source resistance or drain resistance. It should be noted that the problem of contamination of the interface occurs not only in the complementary HEMT of FIG. 5 but also in the DMT of FIG. 4 in which the source and drain regions 29a and 29b are formed as a regrowth crystal region.